Small, portable devices such as personal digital assistants (PDA), multi-function cell phones, digital cameras, music players, etc. have become widely available. These devices use a central processing unit (CPU) or microcontroller and a mass-storage memory such as a hard drive or flash memory. These small devices are often cost and size sensitive.
FIG. 1A is a schematic circuit block diagram illustrating an electronic data storage medium disclosed in the parent application. The electronic data storage medium with fingerprint verification capability can be accessed by external computer 9 using input/output interface circuit 5, which may use a Universal Serial Bus (USB) or similar interface. The electronic data storage medium can be located inside or outside of the external computer. Card reader 6 may be attached to external computer 9 or may act as a substitute for external computer 9 through the host computer link with a Universal-Serial-Bus (USB) USB-Attached-SCSI (UAS) bus, which has one set of two pairs of differential serial buses:
(i) a first pair differential serial bus with a first pin carry + signal and a second pin carry − signal, and
(ii) a second pair differential serial bus with a first pin carry + signal and a second pin carry − signal.
Card reader 6 accepts card body 1. The card reader interface can connect with various standard bus such as Secure Digital (SD) bus, Compact Flash (CF) card, Serial ATA (SATA) bus, Serial SCSI (SAS) bus, etc.
The electronic data storage medium is packaged in card body 1, and includes processing unit 2, memory device 3, security unit 4, and input/output interface circuit 5.
Memory device 3 can be a flash memory device that stores data files. Security and encryption/decryption unit 4 can assist with AES, IEEE 1667, fingerprint, or other kinds of security functions, such as encryption and description and password verification or management. Processing unit 2 connects to other components and can operate in various modes, such as a programming mode, a data retrieving mode, and a data-resetting mode. Power source 7 can be a DC-DC converter that converts from a higher voltage, such as 5 volts, to a lower voltage such as 3.3 or 1.8 volts or some other value that can be used by other units.
The electronic data storage medium packaged in card body 1 includes processing unit 2, memory device 3, and input/output interface circuit 5. While useful, various additions can increase the usefulness of the device. For example, audio playback can be supported. When coupled with security unit 4, the audio playback can have added security features.
Memory device 3 may be a solid-state flash memory rather than a rotational hard drive. Using flash memory provides lighter weight, lower power, and more rigidity than the rotational hard drive. Data files such as audio, video, and text may need security. Also, alternative features such as audio/video capability may replace the fingerprint verification feature on some alternatives of the device.
Hard disks and other mass storage devices are being replaced or supplemented with solid-state mass storage such as flash memories. Flash memories use non-volatile memory cells such as electrically-erasable programmable read-only memory, (EEPROM), but are not randomly accessible at the byte level. Instead, whole pages or sectors of 512 bytes or more are read or written together as a single page. NAND flash memory is commonly used for data storage of blocks. Pages in the same block may have to be erased together, and limitations on writing may exist, such as only being allowed to write each page once between erases.
These small portable electronic devices often are able to connect to a host computer such as a personal computer (PC). While a proprietary connector may be used, a connector for a standard expansion bus is preferable. Universal-Serial Bus (USB) is often used to connect such portable flash-memory devices to a PC.
The USB 3.0 bus standard uses two pairs of differential lines that are time-duplexed, or used for transmission in both directions, but at different times. This may limit performance when data needs to be sent in both directions at the same time. The older USB 2.0 standard provides that the host, such as the PC, controls the bus as the bus master, while USB devices plugged into the host act as slave devices. A USB controller on the host PC generates data transfer transactions and waits for USB devices to respond, either by transmitting requested data to the host, or by writing host data into the USB device's memory.
Often a host system contains several different buses. For example, the host may have a Peripheral Components Interconnect Express (PCIE) bus, a Universal-Serial Bus (USB), an Integrated Device Electronics (IDE) bus, and an AT bus. Peripherals using the Small-Computer System Interface (SCSI) that connect to a host through USB are known as USB-Attached-SCSI (UAS).
Some buses may be enhanced with a revised version of the protocol specification. For example, USB has a version 2.0 and a newer version 3.0 that improves performance by using a full-duplex differential bus, and by eliminating polling. In the future when the interface needs more bandwidths such as 40 Gbps and the copper wires cannot support the necessary speed, high bandwidth fiber with optical, either single-mode or multi-mode, may be used.
For the situation of USB using the optical fiber communication protocol, the flash memory controller of an electronic flash memory card is operable selectively in a programming mode, a data retrieving mode, and a resetting mode. When the flash memory controller is in the programming mode, the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in the flash memory device. A programming mode in which the flash memory controller activates the input/output interface circuit to receive the data file from the host computer, and to store the data file in a physical address of the flash memory device associated with a logical address and transfer length received with a USB optical protocol write command issued from the host computer to the flash memory controller. When the flash memory controller is in the data retrieving mode, the flash memory controller activates the input/output interface circuit to transmit the data file read from the flash memory device to the host computer. A data retrieving mode in which the flash memory controller receives a USB optical protocol read command issued from the host computer including the logical address and transfer length, and activates the input/output interface circuit to transmit the data file read from the physical address of the flash memory device associated with the logical address to the host computer. In the data resetting mode, the data file is erased from the flash memory device. A data resetting mode in which data from one or more memory cells is erased from the flash memory device, wherein the data resetting mode is initiated and performed by the flash memory controller after receiving the USB optical protocol write command using arbitration logic and data that is stored on the flash memory device.
Devices to convert one bus type to another bus type are known as bridges. Legacy host systems are not equipped for the newer bus protocols since these legacy systems are older and were designed before the new bus protocols were available.
Bridges are often slow since all protocol layers may be present and are traversed. Data packets must flow up through the stack of protocol layers and then back down another stack of protocol layers for the other bus. When multiple bus standards are present on a host system, several bridges may be used in series, causing increased delays for multiple successive format conversions by multiple bridge devices.
The parent application, U.S. Ser. No. 11/926,636 described a bridge to the new USB 3.0, or Enhanced USB (EUSB) as it was described therein.
FIG. 1B is a block diagram of host with a EUSB receptacle that supports single-mode EUSB communication. EUSB card 934 could be plugged into EUSB receptacle 950 of host 951. Host 951 could be a cell phone or a digital camera, etc. EUSB receptacle 950 supports single-mode EUSB communication.
Host 951 has a processor system 968 for executing programs including EUSB management and no-polling programs. EUSB protocol processor 960 performs protocol processing such as conversions to EUSB or USB 3.0 over bus 903 for host processor system 968.
EUSB card 934 is a EUSB device with a plug that supports EUSB communication. EUSB card 934 has EUSB protocol processor 980 for executing programs including device initializations and bus-response programs. Single-personality bus interface 973 communicates processed data from EUSB protocol processor 980 using the EUSB protocol to its plug 970. Data is ultimately stored in flash memory 990.
FIG. 1C is a block diagram of a USB UAS card reader with a flash-serial buffer bus in parallel with the CPU bus. One or more flash-card controllers 850, 854 connect to both CPU bus 838 and to flash-serial buffer bus 840. When a flash-memory card is inserted, embedded, or surface mounted into slot A of card reader 200, flash-card controller 850 can transfer data, while when a flash-memory card is inserted into slot B, flash-card controller 854 can transfer data. CPU 10 sends commands over CPU bus 38 to flash-card controllers 850, 854 using their slave ports 851, 855 and CPU master port 815.
What is desired is a solid-state-drive (SSD) that has extra pipes for commands, status, and control to allow data pipes to pass data through with a higher bandwidth. It is desired to use these extra pipes for extended modes of operation. It is desired to use the extra pipes for extended modes such as UAS mode when EUSB, or USB 3.0 is supported. It is also desired to support legacy host systems such as USB 2.0 by sending commands, status, and control through the data pipes for these legacy hosts.